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Digtal Principles and System Design  
Published by Vijay Nicole Imprints Private Limited
Publication Date:  Available in all formats
ISBN: 9789394828261

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Table of contents

Biographical note

Designed as per the latest syllabi of Anna University, this book Digital Principles and System Design provides the basic understanding of digit circuits. It has its emphasis on topics like Boolean Functions, K-Map Method, Quine-McClusky Method, Synchronous and Asynchronous Sequential Circuits, etc.

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Description

Designed as per the latest syllabi of Anna University, this book Digital Principles and System Design provides the basic understanding of digit circuits. It has its emphasis on topics like Boolean Functions, K-Map Method, Quine-McClusky Method, Synchronous and Asynchronous Sequential Circuits, etc.

Table of contents
  • Cover
  • Halftitle Page
  • Title Page
  • Copyright Page
  • Dedication Page
  • Contents
  • Preface
  • Acknowledgements
  • Chapter 1 Number System ad Code
    • 1.1 Introduction
    • 1.2 Digital Signals
      • 1.2.1 Why Binary Numbers are Used?
      • 1.2.2 What is a Digital Signal?
    • 1.3 Digital Computers and Digital System
    • 1.4 Number Systems
    • 1.5 Base Conversions
      • 1.5.1 Binary to Decimal Conversion
      • 1.5.2 Decimal to Binary Conversion
      • 1.5.3 Decimal to Base-r
      • 1.5.4 Base-r to Decimal
      • 1.5.5 Binary to Octal and Binary to Hexadecimal Conversion
      • 1.5.6 Coaversion from Hexadecimal to Octal and Viceversa
    • 1.6 Complements
      • 1.6.1 r’s Complement or Radix Complement
      • 1.6.2 (r-1)’s Complement or Diminished Radix Complement
      • 1.6.3 Additional Method to Determine 10’s and 2’s Complements
    • 1.7 Signed Binary Numbers
    • 1.8 Binary Codes
      • 1.8.1 Straight Binary Code or Simply Binary Code
      • 1.8.2 Gray Code
      • 1.8.3 BCD Code (Binary Coded Decimall
      • 1.8.4 Exccss-3 Code
      • 1.8.5 Error Detecting and Conecting Code
      • 1.8.6 Hamming Code
      • 1.8.7 Determination of Parity Bits
      • 1.8.8 Single Error Correction and Double Error Detection
      • 1.8.9 Alphanumeric Codes [ASCII]
      • 1.8.10 Another Alphanumeric Code [EBCIDIC]
    • 1.9 Binary Arithmetic
      • 1.9.1 Binary Addition
      • 1.9.2 Binary Subtraction
      • 1.9.3 Binary Multiplication
      • 1.9.4 Binary Division
    • 1.10 2’s Complement/1’s Complement Arithmetic
      • 1.10.1 Subtraction with 2’s Complements
      • 1.10.2 Subtraction with 1’s Complement
      • 1.10.3 BCD Addition/Subtraction
      • 1.10.4 Excess-3 Addition/Subtraction
    • Summary
    • Review Questions
    • Problems
  • Chapter 2 Digital Circuit and Boolean Algebra
    • 2.1 Introduction
    • 2.2 Basic Digital Circuits
      • 2.2.1 AND Operation
      • 2.2.2 OR Operation
      • 2.2.3 NOT Operation
      • 2.2.4 NAND and NOR Operations
      • 2.2.5 NAND Operation
      • 2.2.6 NOR Operation
      • 2.2.7 Ex-OR and Ex-NOR Operations
    • 2.3 Boolean Algebra
      • 2.3.1 Basic Definitions
    • 2.4 Basic Theorem and Properties of Boolean Algebra
      • 2.4.1 Proof of Theorems
      • 2.4.2 Postulate 4a Distributive Law
      • 2.4.3 Postulate 4b Distributive Law
    • 2.5 Boolean Function
      • 2.5.1 Explanation
    • 2.6 Canonical and Standard Forms
      • 2.6.1 Minterms and Maxterms
      • 2.6.2 Sum of Minterms
      • 2.6.3 Product of Maxterms
      • 2.6.4 Conversion Between Canonical Forms
      • 2.6.5 Standard Forms
    • 2.7 Other Logic Operations
    • 2.8 Integrated Circuits
      • 2.8.1 Examples of IC Gates
      • 2.8.2 Levels of Integration
    • 2.9 Introduction to Digital Logic Families
      • 2.9.1 Bipolar Logic Families
      • 2.9.2 Unipolar Logic Families
    • 2.10 Brief Discussion of Popular Families
      • 2.10.1 Transistor-Transistor Logic (TTL)
      • 2.10.2 Emitter-Coupled Logic (ECL)
      • 2.10.3 Metal Oxide Semiconductor (MOS) and Complementary Metal Oxide Semiconductor (CMOS)
      • 2.10.4 Characteristics of Digital IC
      • 2.10.5 Current and Voltage Parameters
    • Summary
    • Review Questions
    • Problems
  • Chapters 3 Simplification of Boolean Function
    • 3.1 Introduction
    • 3.2 The K-map Method
      • 3.2.1 Two and Three Variables Maps
      • 3.2.2 Four Variable Map
      • 3.2.3 Representation of Truth Table on K-map
      • 3.2.4 Representation of SOP and POS Form on K-map
    • 3.3 Simplification of Logical Functions Using K-map
      • 3.3.1 Simplification Using Three Variable K-Map
      • 3.3.2 Simplification Using Four Variable K-Map
    • 3.4 Don’t Care Condition
    • 3.5 Prime Implicants and Essential Prime Implicants
    • 3.6 Five and Six Variable Maps
      • 3.6.1 Five Variable Map
      • 3.6.2 Six Variable Map
    • 3.7 Variation of Maps
    • 3.8 NAND and NOR Implementation
      • 3.8.1 Realization of Basic Gates Using NAND and NOR
      • 3.8.2 Graphical Symbol
      • 3.8.3 Two Level Implementation
      • 3.8.4 Multilevel Realizations
      • 3.8.5 Wired Logic
    • 3.9 The Tabulation Method or Quine-McClusky Method
      • 3.9.1 Determination of Prime Implicants in Tabulation Method
    • Summary
    • Review Questions
    • Problems
  • Chapter 4 Combinational Logic Design
    • 4.1 Introduction
    • 4.2 Analysis and Design Procedure
      • 4.2.1 Analysis Procedure
      • 4.2.2 Design Procedure
    • 4.3 Adders/Subtractors
      • 4.3.1 Half Adder/Half Subtracter
      • 4.3.2 Full Adder/Full Subtractor
      • 4.3.3 Binary Parallel Adder
      • 4.3.4 Binary Parallel Subtractor
      • 4.3.5 Binary Adder/Subtractor
      • 4.3.6 Look-ahead Carry Adder
      • 4.3.7 Decimal Adder/Subtractor
    • 4.4 Magnitude Comparator
      • 4.4.1 One-bit Magnitude Comparator
      • 4.4.2 Two-bil Magnitude Comparator
      • 4.4.3 Four-bit Magnitude Comparator
    • 4.5 Decoders and Encoders
      • 4.5.1 Decoders
      • 4.5.2 Three to Eight line Decoder
      • 4.5.3 BCD to Seven Segment Decoder
      • 4.5.4 Encoder
      • 4.5.5 Priority Encoder
    • 4.6 Multiplexer
      • 4.6.1 Boolean Function Implementation Using MUX
      • 4.6.2 Interconnection of Multiplexers
    • 4.7 Demultiplexer
      • 4.7.1 Expansion of DEMUX and Implementation of Boolean Function
    • 4.8 Code Conversion
      • 4.8.1 Binary to Gray Code and Gray Code to Binary Conversion
      • 4.8.2 Binary to Gray Code and Gray Code to Binary Conversion - Conventional Method
      • 4.8.3 Binary to BCD
      • 4.8.4 BCD to Binary Conversion
      • 4.8.5 Eight-bil BCD to Binary Conversion
      • 4.8.6 BCD to Excess-3 Code Conversion
      • 4.8.7 Excess-3 to BCD Code Converter
    • 4.9 Parity Generator/Checker
      • 4.9.1 Parity Generator
      • 4.9.2 Parity Checker
    • 4.10 Memory and Programmable Logic Device
      • 4.10.1 Random Access Memory - RAM
      • 4.10.2 Read Only Memory - ROM
      • 4.10.3 Classification of ROM
      • 4.10.4 ROM as a PLD
      • 4.10.5 PLD Using Array Logic Diagram
    • 4.11 Programmable Logic Array [PLA]
      • 4.11.1 Structure of PLA
    • 4.12 Programmable Array Logic [PAL]
    • 4.13 Functionally Complete Set
    • Summary
    • Review Questions
    • Problems
  • Chapter 5 Flip-Flops
    • 5.1 Introduction
    • 5.2 A One-bit Memory Cell
    • 5.3 S-R Flip-flop
      • 5.3.1 S-R Latch with NAND Gate
      • 5.3.2 NOR S-R bitch
      • 5.3.3 Clocked S-R bitch (S-R Flip Flop)
      • 5.3.4 Characteristic Equation
      • 5.3.5 Timing Diagram
      • 5.3.6 Preset and Clear
    • 5.4 J-K Flip-flop
      • 5.4.1 Characteristic Equation
      • 5.4.2 Timing Diagram
      • 5.4.3 Race Around Condition
      • 5.4.4 Master Slave Flip-flop
    • 5.5 Delay Flip-flop
      • 5.5.1 Characteristic Equation
    • 5.6 T Hip-flop
      • 5.6.1 Characteristic Equation
    • 5.7 Flip-flop Excitation Tables
    • 5.8 Conversion of Flip-flop from One Type to Another Type
    • 5.9 Edge Triggered Flip-flops
    • 5.10 Edge Triggeied S-R Hip-flop
    • 5.11 Applications of Flip-flops
    • Summary
    • Review Questions
    • Problems
  • Chapter 6 Synchronous Sequential Circuit
    • 6.1 Introduction
    • 6.2 Sequential Circuit Model
    • 6.3 Terms and Definitions Used in Sequential Circuit
    • 6.4 Analysis of Synchronous Sequential Circuits
      • 6.4.1 Analysis Procedure
    • 6.5 Synthesis Synchronous Sequential Circuit
      • 6.5.1 Design Procedure
      • 6.5.2 State Reduction
      • 6.5.3 State Assignment
    • Summary
    • Review Questions
    • Problems
  • Chapter 7 Registers and Counters
    • 7.1 Introduction
    • 7.2 Registers
      • 7.2.1 Shift Registers
      • 7.2.2 Serial in Serial-Out [SISO] Shift Register
      • 7.2.3 Serial in Parallel-Out [SIPO] Shift Register
      • 7.2.4 Parallel In Serial-Out [PISO] Shift Register
      • 7.2.5 Parallel In Parallcl-Out [PIPO] Shift Register
      • 7.2.6 Bidirectional Shift Register
    • 7.3 Universal Register
    • 7.4 Applications of Shift Register
      • 7.4.1 Ring Counter
      • 7.4.2 Johnson Counter
    • 7.5 Counters
      • 7.5.1 Ripple Counter
      • 7.5.2 Up/Down Counter
      • 7.5.3 Three Bit Binary Ripple Counter
    • 7.6 Modulus of Counter
      • 7.6.1 Mod - 5 Counter
      • 7.6.2 Mod - 10 Counter or Decade Counter
    • 7.7 Synchronous Counter
      • 7.7.1 Three Bit Synchronous Counter
      • 7.7.2 Up/Down Counter
    • 7.8 Design of Counter
    • Summary
    • Review Questions
    • Problems
  • Chapter 8 Asynchronous Sequential Circuit
    • 8.1 Introduction
    • 8.2 Terms and Definitions Used in Asynchronous Sequential Circuit
    • 8.3 Analysis of Asynchronous Sequential Circuit
      • 8.3.1 Fundamental Mode Circuit without Latches
      • 8.3.2 Circuit with Latches
      • 8.3.3 Implementation of Sequential Circuit with SR Latch
    • 8.4 Design of Asynchronous Sequential Circuit
      • 8.4.1 Primitive Flow Tabic
    • 8.5 State Reduction Techniques
      • 8.5.1 State Reduction of Completely Specified States
      • 8.5.2 State Reduction of Incompletely Specified States
    • 8.6 State Assignment and Unspecified Output Assignment
      • 8.6.1 Races and Cycles
      • 8.6.2 Race Free State Assignments
      • 8.6.3 Unspecified Output Assignment
    • 8.7 Hazards
      • 8.7.1 Circuits with Hazard 36()
      • 8.7.2 Hazard Free Circuit
      • 8.7.3 Effect of Hazards in Asynchronous Sequential Circuit
      • 8.7.4 Essential Hazards
    • 8.8 Design Example
    • Summary
    • Review Questions
    • Problems
  • Chapter 9 VHDL Fundamentals
    • 9.1 Introduction
      • 9.1.1 D Flip-flop Code
    • 9.2 Introduction to VHDL
      • 9.2.1 Entiiy
    • 9.3 Architecture
      • 9.3.1 Structural Style of Modeling
      • 9.3.2 Data Style of Modeling
      • 9.3.3 Behavioural Style of Modeling
      • 9.3.4 Mixed Style of Modeling
    • 9.4 Configuration Declaration
    • 9.5 Generic
    • 9.6 Data Objects
    • 9.7 Examples of VHDL Codes
    • Summary
    • Review Questions
  • Appendix A Two Marks Questions and Answers
  • Appendix B VHDL Reserved Words
  • Appendix C Defined Symbols in VHDL
  • Solved Question Papers
  • References
  • Index
Biographical note
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