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Fundamentals of Computer Architecture  
Published by Vijay Nicole Imprints Private Limited
Publication Date:  Available in all formats
ISBN: 9789393665089

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ISBN: 9788182091122   Price: INR 495.00   

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Table of contents

Biographical note

Fundamentals of Computer Architecture retains all the winning Features of the Advanced Computer Architecture (best selling) book including clear concepts, crisp but adequate coverage, easy readability, and rich pedagogy. This book caters to the one semester first course on Computer Architecture for compute science, IT and electronics and communication engineering students. It also serves as a basic self-study reference for computer professionals interested in computer architecture.

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Description

Fundamentals of Computer Architecture retains all the winning Features of the Advanced Computer Architecture (best selling) book including clear concepts, crisp but adequate coverage, easy readability, and rich pedagogy. This book caters to the one semester first course on Computer Architecture for compute science, IT and electronics and communication engineering students. It also serves as a basic self-study reference for computer professionals interested in computer architecture.

Table of contents
  • Cover
  • Title Page
  • Copyright Page
  • Dedication
  • Contents
  • The authors
  • Preface
  • Chapter 1 Basics of Computers
    • 1.1 Introduction
    • 1.2 Basic Structure of Computer Hardware
    • 1.3 Functional Units
      • 1.3.1 Input/Output Unit
      • 1.3.2 Memory Unit
      • 1.3.3 Central Processing Unit (CPU)
    • 1.4 Basic Operational Concepts
    • 1.5 Computer Components
    • 1.6 Hardware and Software Approaches
    • 1.7 Bus Structures
    • 1.8 Software
    • 1.9 Performance
      • 1.9.1 Basic Performance Measures
      • 1.9.2 Performance Parameters
      • 1.9.3 Pipelining and Parallel Processing
      • 1.9.4 Clock Rate
      • 1.9.5 Compiler
      • 1.9.6 Measuring Performance
      • 1.9.7 Amdahl’s Law
      • 1.9.8 CPU Performance Equation
      • 1.9.9 MIPS, MOPS, FLOPS
      • 1.9.10 Evaluating Performance—Benchmarks
      • 1.9.11 Speculating Performance
    • 1.10 Memory Locations and Addresses
    • 1.11 Memory Operations
    • Summary
    • Review Questions
  • Chapter 2 Instructions and Instruction Sequencing
    • 2.1 Introduction
    • 2.2 Fundamental Factors
      • 2.2.1 Operation Repertoire
      • 2.2.2 Data Types
      • 2.2.3 Format of Instruction
      • 2.2.4 Register
      • 2.2.5 Addressing Modes
    • 2.3 Types of Operands
      • 2.3.1 Addresses
      • 2.3.2 Numbers
      • 2.3.3 Characters
      • 2.3.4 Logical Data
    • 2.4 OP Code Types
      • 2.4.1 Arithmetic
      • 2.4.2 Logical
      • 2.4.3 Data Transfer
      • 2.4.4 Conversion
      • 2.4.5 System Control
      • 2.4.6 Input/Output
      • 2.4.7 Control Transfer
      • 2.4.8 Types of Operations
    • 2.5 Instruction Format
      • 2.5.1 Instruction Set Based on Number of Addresses
    • 2.6 Addressing Techniques
    • 2.7 Addressing Modes
      • 2.7.1 Immediate Addressing
      • 2.7.2 Direct Addressing
      • 2.7.3 Indirect Addressing
      • 2.7.4 Register Addressing
      • 2.7.5 Register Indirect Addressing
      • 2.7.6 Displacement Addressing
      • 2.7.7 Stack Addressing
    • 2.8 Encoding of Addressing Modes
    • 2.9 Assembly Language
    • 2.10 Stacks
    • 2.11 Queues
    • Summary
    • Review Questions
  • Chapter 3 Basic Arithmetic Operations
    • 3.1 Arithmetic Operations
      • 3.1.1 Addition and Subtraction
      • 3.1.2 Multiplication Algorithm
      • 3.1.3 Division Algorithm
      • 3.1.4 Other Algorithms
    • 3.2 Floating-point Representation
      • 3.2.1 Gray Code
      • 3.2.2 Other Decimal Codes
      • 3.2.3 Other Alphanumeric Codes
    • 3.3 Floating-point Arithmetic Operations
      • 3.3.1 Register Configuration
      • 3.3.2 Floating-point Addition and Subtraction
      • 3.3.3 Floating-point Multiplication
      • 3.3.4 Floating-point Division
    • 3.4 Design of Faster Adders
      • 3.4.1 Carry Look-ahead Addition
      • 3.4.2 Higher-level Generate and Propagate Functions
      • 3.4.3 Multiplication of Positive Numbers
      • 3.4.4 Fast Multiplication
      • 3.4.5 Bit-pair Recoding of Multipliers
      • 3.4.6 Carry-save Addition of Summands
    • 3.5 IEEE Standard for Floating-point Numbers
      • 3.5.1 Special Value
      • 3.5.2 Exceptions
    • 3.6 Arithmetic Operation on Floating-point Numbers in IEEE Standard Format
      • 3.6.1 Addition/Subtraction Rule
      • 3.6.2 Multiply Rule
      • 3.6.3 Divide Rule
      • 3.6.4 Guard Bits and Truncation
    • 3.7 Implementing Floating-point Operations
    • Summary
    • Review Questions
  • Chapter 4 Processor Unit
    • 4.1 Design of ALUs
      • 4.1.1 Combinational ALUs
      • 4.1.2 The 4-bit ALU/Function Generator (IC-74181)
      • 4.1.3 Sequential ALU
    • 4.2 Register Files
    • 4.3 Data Path Design
    • 4.4 Bit-slice Processors
      • 4.4.1 Spatial Expansion Bit-slice Processor
      • 4.4.2 Temporal Expansion Bit-slice Processor
      • 4.4.3 AMD 2901 Bit-sliced ALU
    • 4.5 Data Path Implementation
      • 4.5.1 Register Transfers
      • 4.5.2 ALU Operations
    • 4.6 Basic Memory Operations
      • 4.6.1 Read Operation
      • 4.6.2 Write Operation
    • 4.7 Complete Instruction Execution
    • 4.8 Hard-wired Control
      • 4.8.1 A Complete Processor with Hard-wired Control
    • 4.9 Microprogrammed Control
      • 4.9.1 Microinstructions
      • 4.9.2 Sequencing the Microprogram
      • 4.9.3 Wide-branching
      • 4.9.4 Including Next Address in Microinstruction for Better Performance
    • 4.10 Nanoprogramming
    • Summary
    • Review Questions
  • Chapter 5 Advanced Concepts
    • 5.1 Pipelining
      • 5.1.1 Stages in a Pipeline
      • 5.1.2 Latency Vs. Throughput
      • 5.1.3 Characteristics of a Pipeline
      • 5.1.4 Pipeline Computers
      • 5.1.5 Cycle Time
      • 5.1.6 Pipeline Cycle Time
    • 5.2 Design Principles of Pipeline Processors
      • 5.2.1 Instruction Pre-fetch and Branch Handling
      • 5.2.2 Precise Vs. Imprecise Exceptions
      • 5.2.3 Data Buffering and Busing Structures
      • 5.2.4 Job Sequencing and Collision Prevention
    • 5.3 Pipeline Hazards
      • 5.3.1 Pipeline Stalls
    • 5.4 Structural Hazards
      • 5.4.1 Common Types of Structural Hazards
    • 5.5 Data Hazards
      • 5.5.1 Common Occurrence of Data Hazards
      • 5.5.2 Memory Reference Data Hazards
      • 5.5.3 Types of Data Hazards
    • 5.6 Control Hazards
    • 5.7 Overcoming Hazards
      • 5.7.1 Overcoming Structural Hazards
      • 5.7.2 Overcoming Data Hazards
      • 5.7.3 Overcoming Control Hazards
      • 5.7.4 Real Pipelining
    • 5.8 Instruction Set Design and Pipelining
      • 5.8.1 Effects of Addressing Modes
      • 5.8.2 Effects of Condition Codes
      • 5.8.3 Effects of Data Path and Control
    • 5.9 Superscalar
      • 5.9.1 Hardware Requirements
      • 5.9.2 Static Scheduling on a Superscalar Processor
      • 5.9.3 Loop Unrolling and Scheduling on a Dual-issue Processor
      • 5.9.4 Dynamic Scheduling on a Superscalar Processor
      • Summary
      • Review Questions
  • Chapter 6 Memory System
    • 6.1 Characteristics of Memory Systems
      • 6.1.1 Memory Hierarchy
      • 6.1.2 Speed, Size and Cost of Memory
    • 6.2 Basic Concepts of Memory
    • 6.3 Semiconductor RAMs
      • 6.3.1 Organization of Memory Chip
      • 6.3.2 Static RAMS
      • 6.3.3 CMOS Cell
      • 6.3.4 Asynchronous DRAMs
      • 6.3.5 Synchronous DRAM
      • 6.3.6 Latency and Bandwidth
      • 6.3.7 Double-Data-Rate SDRAM (DDR SDRAM)
      • 6.3.8 Static Memory System
      • 6.3.9 Dynamic Memory System
      • 6.3.10 Memory Selection Considerations
      • 6.3.11 Memory Controller
    • 6.4 Read-only Memory (ROM)
      • 6.4.1 PROM
      • 6.4.2 EPROM
      • 6.4.3 EEPROM
      • 6.4.4 Flash Memory
      • 6.4.5 Flash Cards
      • 6.4.6 Flash Drives
    • 6.5 Interleaved Memory
    • 6.6 Cache Memory
    • 6.7 Cache Design Considerations
      • 6.7.1 Cache Size
      • 6.7.2 Mapping Function
      • 6.7.3 Replacement Algorithm
      • 6.7.4 Write Policy
      • 6.7.5 Line Size
      • 6.7.6 Multilevel Caches
      • 6.7.7 Unified Vs. Split Caches
      • 6.7.8 Characterizing Memory Hierarchy
    • 6.8 Virtual Memory
      • 6.8.1 Memory Paging
      • 6.8.2 Memory Segmentation
      • 6.8.3 Paging Vs. Segmentation
      • Summary
      • Review Questions
  • Chapter 7 Input–Output Organization
    • 7.1 Introduction
    • 7.2 I/O Operations
    • 7.3 Programmed I/O
      • 7.3.1 I/O Commands
      • 7.3.2 I/O Instructions
    • 7.4 Interrupt-driven I/O
      • 7.4.1 Processing of Interrupts
      • 7.4.2 Design Issues of Interrupt I/O
      • 7.4.3 Intel 8259A Interrupt Controller
      • 7.4.4 The Intel 8255A Programmable Peripheral Interface (PPI)
    • 7.5 Direct Memory Access (DMA)
    • 7.6 I/O Channel Architecture
      • 7.6.1 Characteristics of I/O Channels
      • Summary
      • Review Questions
  • Chapter 8 Input–Output Devices
    • 8.1 Introduction
    • 8.2 Keyboard
    • 8.3 Mouse
    • 8.4 Trackball, Joystick and Touchpad
    • 8.5 Scanners
    • 8.6 Video Displays
      • 8.6.1 Flat-panel Displays
    • 8.7 Printer
    • 8.8 Magnetic Disk
      • 8.8.1 Disk Read and Write Mechanisms
      • 8.8.2 Data Organization and Formatting
      • 8.8.3 Physical Characteristics
    • 8.9 Optical Devices
      • 8.9.1 CD-ROM
      • 8.9.2 CD-Recordable(CD-R)
      • 8.9.3 CD-Rewritable(CD-RW)
      • 8.9.4 Digital Versatile Disk (DVD)
      • Summary
      • Review Questions
  • Chapter 9 Buses and Standard I/O Interfaces
    • 9.1 Bus Interconnection
    • 9.2 Bus Structure
      • 9.2.1 Multiple-bus Architecture
      • 9.2.2 Traditional Bus Architecture
    • 9.3 Basic Parameters of Bus Design
      • 9.3.1 Types of Buses
      • 9.3.2 Method of Arbitration
      • 9.3.3 Method of Timing
      • 9.3.4 Width of Bus
      • 9.3.5 Type of Data Transfer
    • 9.4 Peripheral Component Interconnect (PCI) Bus
      • 9.4.1 Essential Lines
      • 9.4.2 Optional Lines
      • 9.4.3 PCI Commands
      • 9.4.4 Data Transfer
      • 9.4.5 PCI Bus Arbitration
    • 9.5 Small Computer System Interface (SCSI)
      • 9.5.1 Bus Signals
      • 9.5.2 Arbitration
      • 9.5.3 Selection
      • 9.5.4 Information Transfer
      • 9.5.5 Reselection
    • 9.6 Universal Serial Bus (USB)
      • 9.6.1 Device Characteristics
      • 9.6.2 Plug-and-Play
      • 9.6.3 USB Architecture
      • 9.6.4 Addressing
      • 9.6.5 USB Protocols
      • 9.6.6 Isochronous Traffic on USB
      • 9.6.7 Electrical Characteristics of USB
    • 9.7 Conclusion
    • Summary
    • Review Questions
  • Short Questions and Answers
  • Index
Biographical note

K A Parthasarathy, M.Tech., M.I.S.T.E. is Professor and Head of the Department of CSE and IT in Asan Memorial College of Engineering and Technology, Chengalpattu, Tamilnadu. He has over 24 years of industrial experience in leading hardware companies like IBM International, CMC ltd, and software organization like Fidelity Computers.

P Senthil Kumar. M.E(Computer Science and Engineering) is working as Lecturer in the Department of Computer Science and Engineering at Asan Memorial College of Engineering and Technology, Chengalpattu. His areas of interest include Image Processing, Multimedia, Operating Systems and Computer Networks.

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