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VLSI Design, 4e (AU R - 2017)
VLSI Design, 4e (AU R - 2017)
ISBN 9789394524903
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Table of contents

Biographical note

User Reviews

This book is designed to address the syllabi requirements of the latest Anna University Regulations 2017. It presents concepts in a simple fashion and is structured to help students understand the subject with ease.

  • Cover
  • Title Page
  • Copyright Page
  • Dedication
  • Contents
  • Syllabus
  • Preface
  • Acknowledgements
  • List of Abbreviations
  • Chapter 1 Introduction to mos Transistor
    • 1.1 Introduction
      • 1.1.1 Evolution
      • 1.1.2 Integration
      • 1.1.3 Moore’s Law
      • 1.1.4 VLSI Design Flow
    • 1.2 MOS Transistor
      • 1.2.1 nMOS
      • 1.2.2 pMOS
      • 1.2.3 Threshold Voltage (Vt)
      • 1.2.4 Modes of Operation of nMOS Transistor
      • 1.2.5 Behavior of nMOS with Different Voltages
    • 1.3 CMOS Logic
      • 1.3.1 Inverter
      • 1.3.2 NAND Gate
      • 1.3.3 Combinational Logic
      • 1.3.4 NOR Gate
      • 1.3.5 Compound Gates
      • 1.3.6 Pass Transistors and Transmission Gates
    • 1.4 Layout Design Rules
    • 1.5 Gate Layouts
    • 1.6 Stick Diagrams
      • 1.6.1 Examples of Layout and Stick Diagrams
    • 1.7 Ideal I-V Characteristics
      • 1.7.1 Cut-off Region
      • 1.7.2 Linear Region
      • 1.7.3 Saturation Region
    • 1.8 C-V Characteristics
      • 1.8.1 Simple MOS Capacitance Model
      • 1.8.2 Detailed MOS Capacitance Model
      • 1.8.3 Detailed MOS Diffusion Capacitance Model
    • 1.9 Nonideal I-V Effects
      • 1.9.1 Velocity Saturation and Mobility Degradation
      • 1.9.2 Channel Length Modulation
      • 1.9.3 Body Effect
      • 1.9.4 Sub-threshold Condition
      • 1.9.5 Junction Leakage
      • 1.9.6 Tunneling
      • 1.9.7 Temperature Dependence
      • 1.9.8 Geometry Dependence
    • 1.10 DC Transfer Characteristics
      • 1.10.1 Complementary CMOS Inverter DC Characteristics
      • 1.10.2 Beta Ratio Effect
      • 1.10.3 Noise Margin
      • 1.10.4 Ratioed Inverter Transfer Function
      • 1.10.5 Pass Transistor DC Characteristics
      • 1.10.6 Tristate Inverter
    • 1.11 Delay Estimation
      • 1.11.1 RC Delay Models
      • 1.11.2 Linear Delay Model
      • 1.11.3 Logical Effort
      • 1.11.4 Parasitic Delay
    • 1.12 Logical Effort and Transistor Sizing
      • 1.12.1 Delay in a Logic Gate
      • 1.12.2 Delay in Multistage Logic Networks
      • 1.12.3 Choosing the Best Number of Stages
    • 1.13 Scaling
      • 1.13.1 Lambda based Design Rule
      • 1.13.2 Transistor Scaling
      • 1.13.3 Scaling Factors for Device Parameters
      • 1.13.4 Interconnect Scaling
      • 1.13.5 International Technology Roadmap for Semiconductors
      • 1.13.6 Impacts on Design
      • 1.13.7 Limitations of Scaling
      • 1.13.8 CMOS Inverter Scaling
    • Review Questions
  • Chapter 2 Combinational mos Logic Circuits
    • 2.1 Introduction
    • 2.2 Static CMOS Design
      • 2.2.1 Concept of Complementary CMOS Gates
      • 2.2.2 Points to Remember while Constructing with PDN and PUN
      • 2.2.3 Static Properties of Complementary CMOS Gates
      • 2.2.4 Propagation Delay of Complementary CMOS Gates
      • 2.2.5 Design Techniques for Large Fan-in
      • 2.2.6 Optimizing Performance in Combinational Networks
      • 2.2.7 Power Consumption in CMOS Logic Gates
      • 2.2.8 Design Techniques to Reduce Switching Activity
    • 2.3 Ratioed Circuits
      • 2.3.1 Pseudo-nMOS Logic
      • 2.3.2 Ganged CMOS Logic
      • 2.3.3 Source Follower Pull-up Logic
      • 2.3.4 Cascode Voltage Switch Logic
    • 2.4 Dynamic Circuit
      • 2.4.1 Domino Logic
      • 2.4.2 Dual-Rail Domino Logic
      • 2.4.3 Keepers
      • 2.4.4 Secondary Precharge Devices
      • 2.4.5 Logical Effort of Dynamic Paths
      • 2.4.6 Multiple-Output Domino Logic
      • 2.4.7 NP and Zipper Domino
    • 2.5 Pass Transistor Logic
      • 2.5.1 Voltage Transfer Characteristics of Pass Transistor AND Gate
      • 2.5.2 Transmission Gates
      • 2.5.1 CMOS with Transmission Gates
      • 2.5.4 Complementary Pass Transistor Logic
      • 2.5.5 Efficient Pass Transistor Logic
      • 2.5.6 Lean Integration with Pass Transistor
      • 2.5.7 Other Pass Transistor Families
      • 2.5.8 Performance of Pass Transistor and Transmission Gate Logic
      • 2.5.9 Delay in Chain of Transmission Gates
    • 2.6 Circuit Pitfalls
      • 2.6.1 Threshold Drops
      • 2.6.2 Ratio Failures
      • 2.6.3 Leakage
      • 2.6.4 Charge Sharing
      • 2.6.5 Power Supply Noise
      • 2.6.6 Coupling
      • 2.6.7 Minority Carrier Injection
      • 2.6.8 Back-gate Coupling
      • 2.6.9 Diffusion Input Noise Sensitivity
      • 2.6.10 Race Conditions
      • 2.6.11 Delay Matching
      • 2.6.12 Metastability
      • 2.6.13 Hot Spots
      • 2.6.14 Soft Errors
      • 2.6.15 Process Sensitivity
    • 2.7 Power
      • 2.7.1 Dynamic Power
      • 2.7.2 Static Power
      • 2.7.3 Low Power Architecture
    • Review Questions
  • Chapter 3 Sequential Circuit Design
    • 3.1 Introduction
      • 3.1.1 Timing Metrics for Sequential Circuits
      • 3.1.2 Classification of Memory Elements
    • 3.2 Static Latches and Registers
      • 3.2.1 Bistability Principle
      • 3.2.2 Multiplexer-based Latches
      • 3.2.3 Master Slave Edge Triggered Register
      • 3.2.4 Low Voltage Static Latches
      • 3.2.5 Static SR Flip-flops
    • 3.3 Dynamic Latches and Registers
      • 3.3.1 Dynamic Transmission Gate Edge Triggered Registers
      • 3.3.2 C2MOoS with Clock Skew Insensitive Approach
      • 3.3.3 True Single Phase Clocked Register
    • 3.4 Pulse Registers
    • 3.5 Sense Amplifier based Register
    • 3.6 Pipelines
      • 3.6.1 Latch-versus Register-based Pipelines
      • 3.6.2 NORA-CMOS based Pipelines
    • 3.7 Schmitt Trigger
    • 3.8 Monostable Sequential Circuits
    • 3.9 Astable Sequential Circuits
    • 3.10 Timing Issues
      • 3.10.1 Timing Classification of Digital Systems
      • 3.10.2 Synchronous Design
    • Review Questions
  • Chapter 4 Designing Arithmetic Building Blocks and Subsystem
    • 4.1 Introduction
    • 4.2 Datapath Circuits
    • 4.3 Adders
      • 4.3.1 Binary Adder
      • 4.3.2 Full Adders
      • 4.3.3 Binary Adder Design
    • 4.4 Multipliers
      • 4.4.1 Partial-Product Generation
      • 4.4.2 Partial-Product Accumulation
      • 4.4.3 Final Addition
    • 4.5 Shifters
      • 4.5.1 Barrel Shifter
      • 4.5.2 Logarithmic Shifter
    • 4.6 Accumulators
      • 4.6.1 Arithmetic Logic Unit
    • 4.7 Power and Speed Tradeoff
      • 4.7.1 Design Time Power Reduction
      • 4.7.2 Run Time Power Management
      • 4.7.3 Power Reduction in Standby or Sleep Mode
    • 4.8 Case Study: Design as a Tradeoff
    • 4.9 Memory Architecture and Building Blocks
      • 4.9.1 N-word Memory Architecture
      • 4.9.2 Array Structured Memory Architecture
      • 4.9.3 Hierarchical Memory Architecture
      • 4.9.4 Content Addressable Memory Architecture
    • 4.10 Memory Core
      • 4.10.1 Read-Only Memory
      • 4.10.2 Nonvolatile Memory
      • 4.10.3 Read-Write Memory
      • 4.10.4 Associative Memory
    • 4.11 Memory Control Circuits
      • 4.11.1 Address Decoders
      • 4.11.2 Sense Amplifiers
      • 4.11.3 Voltage References
      • 4.11.4 Drivers/Buffers
      • 4.11.5 Timing and Control
    • Review Questions
  • Chapter 5 Implementation Strategies and Testing
    • 5.1 Introduction
    • 5.2 Types of ASIC
      • 5.2.1 Full Custom ASICs
      • 5.2.2 Standard Cell-based ASICs
      • 5.2.3 Gate Array-based ASICs
      • 5.2.4 Channeled Gate Array
      • 5.2.5 Channelless Gate Array
      • 5.2.6 Structured Gate Array
      • 5.2.7 Programmable Logic Devices
      • 5.2.8 Field Programmable Gate Arrays
    • 5.3 ASIC Design Flow
    • 5.4 FPGA Building Block Architectures
      • 5.4.1 Actel ACT
      • 5.4.2 Xilinx LCA
      • 5.4.3 Altera FLEX
      • 5.4.4 Altera MAX
      • 5.4.5 Altera MAX 7000
    • 5.5 FPGA Interconnect Routing Procedures
      • 5.5.1 Actel ACT
      • 5.5.2 Xilinx LCA
      • 5.5.3 Xilinx EPLD
      • 5.5.4 Altera MAX 5000 and 7000
      • 5.5.5 Altera MAX 9000
      • 5.5.6 Altera FLEX
    • 5.6 Manufacturing Test Principles
      • 5.6.1 Fault Models
      • 5.6.2 Observability
      • 5.6.3 Controllability
      • 5.6.4 Fault Coverage
      • 5.6.5 Automatic Test Pattern Generation (ATPG)
      • 5.6.6 Delay Fault Testing
    • 5.7 Design for Testability (DFT)
      • 5.7.1 Ad hoc Testing
      • 5.7.2 Scan Design
      • 5.7.3 Built-In Self-Test (BIST)
      • 5.7.4 IDDQ Testing
      • 5.7.5 Design for Manufacturability
    • 5.8 Boundary Scan
      • 5.8.1 Test Access Port (TAP) Architecture
    • Review Questions
  • University Question Paper
  • Index
null
Comments should not be blank
Rating
Description

This book is designed to address the syllabi requirements of the latest Anna University Regulations 2017. It presents concepts in a simple fashion and is structured to help students understand the subject with ease.

Table of contents
  • Cover
  • Title Page
  • Copyright Page
  • Dedication
  • Contents
  • Syllabus
  • Preface
  • Acknowledgements
  • List of Abbreviations
  • Chapter 1 Introduction to mos Transistor
    • 1.1 Introduction
      • 1.1.1 Evolution
      • 1.1.2 Integration
      • 1.1.3 Moore’s Law
      • 1.1.4 VLSI Design Flow
    • 1.2 MOS Transistor
      • 1.2.1 nMOS
      • 1.2.2 pMOS
      • 1.2.3 Threshold Voltage (Vt)
      • 1.2.4 Modes of Operation of nMOS Transistor
      • 1.2.5 Behavior of nMOS with Different Voltages
    • 1.3 CMOS Logic
      • 1.3.1 Inverter
      • 1.3.2 NAND Gate
      • 1.3.3 Combinational Logic
      • 1.3.4 NOR Gate
      • 1.3.5 Compound Gates
      • 1.3.6 Pass Transistors and Transmission Gates
    • 1.4 Layout Design Rules
    • 1.5 Gate Layouts
    • 1.6 Stick Diagrams
      • 1.6.1 Examples of Layout and Stick Diagrams
    • 1.7 Ideal I-V Characteristics
      • 1.7.1 Cut-off Region
      • 1.7.2 Linear Region
      • 1.7.3 Saturation Region
    • 1.8 C-V Characteristics
      • 1.8.1 Simple MOS Capacitance Model
      • 1.8.2 Detailed MOS Capacitance Model
      • 1.8.3 Detailed MOS Diffusion Capacitance Model
    • 1.9 Nonideal I-V Effects
      • 1.9.1 Velocity Saturation and Mobility Degradation
      • 1.9.2 Channel Length Modulation
      • 1.9.3 Body Effect
      • 1.9.4 Sub-threshold Condition
      • 1.9.5 Junction Leakage
      • 1.9.6 Tunneling
      • 1.9.7 Temperature Dependence
      • 1.9.8 Geometry Dependence
    • 1.10 DC Transfer Characteristics
      • 1.10.1 Complementary CMOS Inverter DC Characteristics
      • 1.10.2 Beta Ratio Effect
      • 1.10.3 Noise Margin
      • 1.10.4 Ratioed Inverter Transfer Function
      • 1.10.5 Pass Transistor DC Characteristics
      • 1.10.6 Tristate Inverter
    • 1.11 Delay Estimation
      • 1.11.1 RC Delay Models
      • 1.11.2 Linear Delay Model
      • 1.11.3 Logical Effort
      • 1.11.4 Parasitic Delay
    • 1.12 Logical Effort and Transistor Sizing
      • 1.12.1 Delay in a Logic Gate
      • 1.12.2 Delay in Multistage Logic Networks
      • 1.12.3 Choosing the Best Number of Stages
    • 1.13 Scaling
      • 1.13.1 Lambda based Design Rule
      • 1.13.2 Transistor Scaling
      • 1.13.3 Scaling Factors for Device Parameters
      • 1.13.4 Interconnect Scaling
      • 1.13.5 International Technology Roadmap for Semiconductors
      • 1.13.6 Impacts on Design
      • 1.13.7 Limitations of Scaling
      • 1.13.8 CMOS Inverter Scaling
    • Review Questions
  • Chapter 2 Combinational mos Logic Circuits
    • 2.1 Introduction
    • 2.2 Static CMOS Design
      • 2.2.1 Concept of Complementary CMOS Gates
      • 2.2.2 Points to Remember while Constructing with PDN and PUN
      • 2.2.3 Static Properties of Complementary CMOS Gates
      • 2.2.4 Propagation Delay of Complementary CMOS Gates
      • 2.2.5 Design Techniques for Large Fan-in
      • 2.2.6 Optimizing Performance in Combinational Networks
      • 2.2.7 Power Consumption in CMOS Logic Gates
      • 2.2.8 Design Techniques to Reduce Switching Activity
    • 2.3 Ratioed Circuits
      • 2.3.1 Pseudo-nMOS Logic
      • 2.3.2 Ganged CMOS Logic
      • 2.3.3 Source Follower Pull-up Logic
      • 2.3.4 Cascode Voltage Switch Logic
    • 2.4 Dynamic Circuit
      • 2.4.1 Domino Logic
      • 2.4.2 Dual-Rail Domino Logic
      • 2.4.3 Keepers
      • 2.4.4 Secondary Precharge Devices
      • 2.4.5 Logical Effort of Dynamic Paths
      • 2.4.6 Multiple-Output Domino Logic
      • 2.4.7 NP and Zipper Domino
    • 2.5 Pass Transistor Logic
      • 2.5.1 Voltage Transfer Characteristics of Pass Transistor AND Gate
      • 2.5.2 Transmission Gates
      • 2.5.1 CMOS with Transmission Gates
      • 2.5.4 Complementary Pass Transistor Logic
      • 2.5.5 Efficient Pass Transistor Logic
      • 2.5.6 Lean Integration with Pass Transistor
      • 2.5.7 Other Pass Transistor Families
      • 2.5.8 Performance of Pass Transistor and Transmission Gate Logic
      • 2.5.9 Delay in Chain of Transmission Gates
    • 2.6 Circuit Pitfalls
      • 2.6.1 Threshold Drops
      • 2.6.2 Ratio Failures
      • 2.6.3 Leakage
      • 2.6.4 Charge Sharing
      • 2.6.5 Power Supply Noise
      • 2.6.6 Coupling
      • 2.6.7 Minority Carrier Injection
      • 2.6.8 Back-gate Coupling
      • 2.6.9 Diffusion Input Noise Sensitivity
      • 2.6.10 Race Conditions
      • 2.6.11 Delay Matching
      • 2.6.12 Metastability
      • 2.6.13 Hot Spots
      • 2.6.14 Soft Errors
      • 2.6.15 Process Sensitivity
    • 2.7 Power
      • 2.7.1 Dynamic Power
      • 2.7.2 Static Power
      • 2.7.3 Low Power Architecture
    • Review Questions
  • Chapter 3 Sequential Circuit Design
    • 3.1 Introduction
      • 3.1.1 Timing Metrics for Sequential Circuits
      • 3.1.2 Classification of Memory Elements
    • 3.2 Static Latches and Registers
      • 3.2.1 Bistability Principle
      • 3.2.2 Multiplexer-based Latches
      • 3.2.3 Master Slave Edge Triggered Register
      • 3.2.4 Low Voltage Static Latches
      • 3.2.5 Static SR Flip-flops
    • 3.3 Dynamic Latches and Registers
      • 3.3.1 Dynamic Transmission Gate Edge Triggered Registers
      • 3.3.2 C2MOoS with Clock Skew Insensitive Approach
      • 3.3.3 True Single Phase Clocked Register
    • 3.4 Pulse Registers
    • 3.5 Sense Amplifier based Register
    • 3.6 Pipelines
      • 3.6.1 Latch-versus Register-based Pipelines
      • 3.6.2 NORA-CMOS based Pipelines
    • 3.7 Schmitt Trigger
    • 3.8 Monostable Sequential Circuits
    • 3.9 Astable Sequential Circuits
    • 3.10 Timing Issues
      • 3.10.1 Timing Classification of Digital Systems
      • 3.10.2 Synchronous Design
    • Review Questions
  • Chapter 4 Designing Arithmetic Building Blocks and Subsystem
    • 4.1 Introduction
    • 4.2 Datapath Circuits
    • 4.3 Adders
      • 4.3.1 Binary Adder
      • 4.3.2 Full Adders
      • 4.3.3 Binary Adder Design
    • 4.4 Multipliers
      • 4.4.1 Partial-Product Generation
      • 4.4.2 Partial-Product Accumulation
      • 4.4.3 Final Addition
    • 4.5 Shifters
      • 4.5.1 Barrel Shifter
      • 4.5.2 Logarithmic Shifter
    • 4.6 Accumulators
      • 4.6.1 Arithmetic Logic Unit
    • 4.7 Power and Speed Tradeoff
      • 4.7.1 Design Time Power Reduction
      • 4.7.2 Run Time Power Management
      • 4.7.3 Power Reduction in Standby or Sleep Mode
    • 4.8 Case Study: Design as a Tradeoff
    • 4.9 Memory Architecture and Building Blocks
      • 4.9.1 N-word Memory Architecture
      • 4.9.2 Array Structured Memory Architecture
      • 4.9.3 Hierarchical Memory Architecture
      • 4.9.4 Content Addressable Memory Architecture
    • 4.10 Memory Core
      • 4.10.1 Read-Only Memory
      • 4.10.2 Nonvolatile Memory
      • 4.10.3 Read-Write Memory
      • 4.10.4 Associative Memory
    • 4.11 Memory Control Circuits
      • 4.11.1 Address Decoders
      • 4.11.2 Sense Amplifiers
      • 4.11.3 Voltage References
      • 4.11.4 Drivers/Buffers
      • 4.11.5 Timing and Control
    • Review Questions
  • Chapter 5 Implementation Strategies and Testing
    • 5.1 Introduction
    • 5.2 Types of ASIC
      • 5.2.1 Full Custom ASICs
      • 5.2.2 Standard Cell-based ASICs
      • 5.2.3 Gate Array-based ASICs
      • 5.2.4 Channeled Gate Array
      • 5.2.5 Channelless Gate Array
      • 5.2.6 Structured Gate Array
      • 5.2.7 Programmable Logic Devices
      • 5.2.8 Field Programmable Gate Arrays
    • 5.3 ASIC Design Flow
    • 5.4 FPGA Building Block Architectures
      • 5.4.1 Actel ACT
      • 5.4.2 Xilinx LCA
      • 5.4.3 Altera FLEX
      • 5.4.4 Altera MAX
      • 5.4.5 Altera MAX 7000
    • 5.5 FPGA Interconnect Routing Procedures
      • 5.5.1 Actel ACT
      • 5.5.2 Xilinx LCA
      • 5.5.3 Xilinx EPLD
      • 5.5.4 Altera MAX 5000 and 7000
      • 5.5.5 Altera MAX 9000
      • 5.5.6 Altera FLEX
    • 5.6 Manufacturing Test Principles
      • 5.6.1 Fault Models
      • 5.6.2 Observability
      • 5.6.3 Controllability
      • 5.6.4 Fault Coverage
      • 5.6.5 Automatic Test Pattern Generation (ATPG)
      • 5.6.6 Delay Fault Testing
    • 5.7 Design for Testability (DFT)
      • 5.7.1 Ad hoc Testing
      • 5.7.2 Scan Design
      • 5.7.3 Built-In Self-Test (BIST)
      • 5.7.4 IDDQ Testing
      • 5.7.5 Design for Manufacturability
    • 5.8 Boundary Scan
      • 5.8.1 Test Access Port (TAP) Architecture
    • Review Questions
  • University Question Paper
  • Index
Biographical note
null
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