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VLSI Design  
Published by Vijay Nicole Imprints Private Limited
Publication Date:  Available in all formats
ISBN: 9789394524880

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Table of contents

Biographical note

This book VLSI Design covers the syllabus of Anna University in toto. The book presents concepts in a simple fashion and is structured to help students understand the subject with ease.

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Description

This book VLSI Design covers the syllabus of Anna University in toto. The book presents concepts in a simple fashion and is structured to help students understand the subject with ease.

Table of contents
  • Cover
  • Halftitle Page
  • Title Page
  • Copyright Page
  • Dedication
  • SYLLABUS
  • Table of Contents
  • Preface
  • Acknowledgements
  • List of Abbreviations
  • CHAPTER 1 CMOS TECHNOLOGY
    • 1.0 Introduction
    • 1.1 A Brief History
      • 1.1.1 Evolution
      • 1.1.2 Integration
      • 1.1.3 Moore’s Law
    • 1.2 MOS Transistor
      • 1.2.1 nMOS
      • 1.2.2 pMOS
      • 1.2.3 Threshold Voltage
      • 1.2.4 Modes of Operation of nMOS Transistor
      • 1.2.5 Behavior of nMOS with Different Voltages
      • 1.2.6 CMOS Logic
    • 1.3 Ideal I-V Characteristics
      • 1.3.1 Cut-off Region
      • 1.3.2 Linear Region
      • 1.3.3 Saturation Region
    • 1.4 C-V Characteristics
      • 1.4.1 Simple MOS Capacitance Model
      • 1.4.2 Detailed MOS Capacitance Model
      • 1.4.3 Detailed MOS Diffusion Capacitance Model
    • 1.5 Nonideal I-V Effects
      • 1.5.1 Velocity Saturation and Mobility Degradation
      • 1.5.2 Channel Length Modulation
      • 1.5.3 Body Effect
      • 1.5.4 Sub-threshold Condition
      • 1.5.5 Junction Leakage
      • 1.5.6 Tunneling
      • 1.5.7 Temperature Dependence
      • 1.5.8 Geometry Dependence
    • 1.6 DC Transfer Characteristics
      • 1.6.1 Complementary CMOS Inverter DC Characteristics
      • 1.6.2 Beta Ratio Effect
      • 1.6.3 Noise Margin
      • 1.6.4 Ratioed Inverter Transfer Function
      • 1.6.5 Pass Transistor DC Characteristics
      • 1.6.6 Tristate Inverter
    • 1.7 CMOS Technologies
      • 1.7.1 Manufacturing Steps Involved in the Formation of CMOS Transistor
      • 1.7.2 CMOS Processing Technology
    • 1.8 Layout Design Rules
      • 1.8.1 Design Rule Background
      • 1.8.2 Scribe Line and Other Structures
      • 1.8.3 MOSIS Scalable CMOS Design Rules
      • 1.8.4 Micron Design Rules
    • 1.9 CMOS Process Enhancements
      • 1.9.1 Transistors
      • 1.9.2 Interconnect
      • 1.9.3 Circuit Elements
      • 1.9.4 Beyond Conventional CMOS
    • 1.10 Technology-related CAD Issues
      • 1.10.1 Design Rule Checking
      • 1.10.2 Circuit Extraction
    • 1.11 Manufacturing Issues
      • 1.11.1 Antenna Rules
      • 1.11.2 Layer Density Rules
      • 1.11.3 Resolution Enhancement Rules
    • Review Questions
      • Short Question
      • Brief Questions
  • CHAPTER 2 CIRCUIT CHARACTERIZATION AND SIMULATION
    • 2.0 Introduction
    • 2.1 Delay Estimation
      • 2.1.1 RC Delay Models
      • 2.1.2 Linear Delay Model
      • 2.1.3 Logical Effort
      • 2.1.4 Parasitic Delay
    • 2.2 Logical Effort and Transistor Sizing
      • 2.2.1 Delay in a Logic Gate
      • 2.2.2 Delay in Multistage Logic Networks
      • 2.2.3 Choosing the Best Number of Stages
    • 2.3 Power Dissipation
      • 2.3.1 Static Dissipation
      • 2.3.2 Dynamic Dissipation
      • 2.3.3 Low-power Design
    • 2.4 Interconnect
      • 2.4.1 Resistance
      • 2.4.2 Capacitance
      • 2.4.3 Delay
      • 2.4.4 Crosstalk
    • 2.5 Design Margin
      • 2.5.1 Supply Voltage
      • 2.5.2 Temperature
      • 2.5.3 Process Variation
      • 2.5.4 Design Corners
    • 2.6 Reliability
      • 2.6.1 Electromigration
      • 2.6.2 Self-heating
      • 2.6.3 Hot Carriers
      • 2.6.4 Latch-up
      • 2.6.5 Overvoltage Failure
      • 2.6.6 Soft Errors
      • 2.6.7 Circuit Pitfalls
    • 2.7 Scaling
      • 2.7.1 Transistor Scaling
      • 2.7.2 Interconnect Scaling
      • 2.7.3 International Technology Roadmap for Semiconductors
      • 2.7.4 Impacts on Design
    • 2.8 SPICE Tutorial
    • 2.9 Device Models
      • 2.9.1 Level 1 Models
      • 2.9.2 Level 2 and 3 Models
      • 2.9.3 BSIM Models
      • 2.9.4 Diffusion Capacitance Models
      • 2.9.5 Design Corners
    • 2.10 Device Characterization
      • 2.10.1 I-V Characteristics
      • 2.10.2 Threshold Voltage
      • 2.10.3 Gate Capacitance
      • 2.10.4 Parasitic Capacitance
      • 2.10.5 Effective Resistance
    • 2.11 Circuit Characterization
      • 2.11.1 Path Simulations
      • 2.11.2 DC Transfer Characteristics
      • 2.11.3 Logical Effort
      • 2.11.4 Power and Energy
      • 2.11.5 Simulating Mismatches
      • 2.11.6 Monte Carlo Simulation
    • 2.12 Interconnect Simulation
    • Review Questions
      • Short Questions
      • Brief Questions
  • CHAPTER 3 COMBINATIONAL AND SEQUENTIAL CIRCUIT DESIGN
    • 3.0 Introduction
    • 3.1 Circuit Families
      • 3.1.1 Static CMOS
      • 3.1.2 Ratioed Circuits
      • 3.1.3 Cascode Voltage Switch Logic
      • 3.1.4 Dynamic Circuits
      • 3.1.5 Pass Transistor Circuits
      • 3.1.6 Differential Circuits
      • 3.1.7 Sense Amplifier Circuits
      • 3.1.8 BiCMOS Circuits
    • 3.2 Low Power Logic Design
    • 3.3 Comparison of Circuit Families
    • 3.4 Sequencing Static Circuits
      • 3.4.1 Sequencing Methods
      • 3.4.2 Max-Delay Constraints
      • 3.4.3 Min-Delay Constraints
      • 3.4.4 Time Borrowing
      • 3.4.5 Clock Skew
    • 3.5 Circuit Design of Latches and Flip-flops
      • 3.5.1 Conventional CMOS Latches
      • 3.5.2 Conventional CMOS Flip-flops
      • 3.5.3 Pulsed Latches
      • 3.5.4 Resettable Latches and Flip-flops
      • 3.5.5 Enabled Latches and Flip-flops
      • 3.5.6 Incorporating Logic into Latches
      • 3.5.7 Klass Semidynamic Flip-flop
      • 3.5.8 Differential Flip-flops
      • 3.5.9 True Single-Phase Clock Latches and Flip-flops
    • 3.6 Static Sequencing Element Methodology
      • 3.6.1 Choice of Elements
      • 3.6.2 Low-power Sequential Design
      • 3.6.3 Two-phase Timing Types
      • 3.6.4 Characterizing Sequencing Element Delays
    • 3.7 Sequencing Dynamic Circuits
      • 3.7.1 Traditional Domino Circuits
      • 3.7.2 Skew-tolerant Domino Circuits
    • 3.8 Synchronizers
      • 3.8.1 Metastability
      • 3.8.2 Simple Synchronizer
      • 3.8.3 Communication Between Asynchronous Clock Domains
      • 3.8.4 Common Synchronizer Mistakes
      • 3.8.5 Arbiters
    • Review Questions
      • Short Questions
      • Brief Questions
  • CHAPTER 4 CMOS TESTING
    • 4.0 Introduction
    • 4.1 Need for Testing
      • 4.1.1 Functionality Tests or Logic Verification
      • 4.1.2 Digital Debugging Hints
      • 4.1.3 Manufacturing Tests
    • 4.2 Testers, Text Fixtures and Test Programs
      • 4.2.1 Testers and Test Fixtures
      • 4.2.2 Test Programs
      • 4.2.3 Handlers
    • 4.3 Logic Verification Principles
      • 4.3.1 Test Benches and Harnesses
      • 4.3.2 Regression Testing
      • 4.3.3 Version Control
      • 4.3.4 Bug Tracking
    • 4.4 Silicon Debug Principles
    • 4.5 Manufacturing Test Principles
      • 4.5.1 Fault Models
      • 4.5.2 Observability
      • 4.5.3 Controllability
      • 4.5.4 Fault Coverage
      • 4.5.5 Automatic Test Pattern Generation (ATPG)]
      • 4.5.6 Delay Fault Testing
    • 4.6 Design for Testability (DFT)
      • 4.6.1 Ad hoc Testing
      • 4.6.2 Scan Design
      • 4.6.3 Built-In Self-Test (BIST)
      • 4.6.4 IDDQ Testing
      • 4.6.5 Design for Manufacturability
    • 4.7 Boundary Scan
      • 4.7.1 Test Access Port (TAP) Architecture
    • Review Questions
      • Short Questions
      • Brief Questions
  • CHAPTER 5 SPECIFICATION USING VERILOG HDL
    • 5.0 Introduction
    • 5.1 Features of Verilog HDL
      • 5.1.1 Advantages
      • 5.1.2 Design Methodologies
      • 5.1.3 Modules
      • 5.1.4 Instances
      • 5.1.5 Test Bench
    • 5.2 Basic Concepts
      • 5.2.1 Keywords
      • 5.2.2 Identifiers
      • 5.2.3 Escaped Identifiers
      • 5.2.4 Whitespace
      • 5.2.5 Comments
      • 5.2.6 Value Set
      • 5.2.7 Strings
      • 5.2.8 Nets
      • 5.2.9 Registers
      • 5.2.10 Vectors
      • 5.2.11 Integer
      • 5.2.12 Real
      • 5.2.13 Time
      • 5.2.14 Arrays
      • 5.2.15 Memories
      • 5.2.16 Parameters
      • 5.2.17 System Tasks
      • 5.2.18 Compiler Directives
      • 5.2.19 Operators
    • 5.3 Gate-Level Modeling
      • 5.3.1 Gate Primitives
      • 5.3.2 Gate Delays
    • 5.4 Dataflow Modeling
      • 5.4.1 Continuous Assignments
      • 5.4.2 Delays
    • 5.5 Behavioral Modeling
      • 5.5.1 Structured Procedures
      • 5.5.2 Procedural Assignments
      • 5.5.3 Timing Controls
      • 5.5.4 Conditional Statements
      • 5.5.5 Multiway Branching
      • 5.5.6 Loops
      • 5.5.7 Sequential and Parallel Blocks
      • 5.5.8 Procedural Continuous Assignments
    • 5.6 Switch-Level Modeling
      • 5.6.1 MOS Switches
      • 5.6.2 CMOS Switches
      • 5.6.3 Bidirectional Switches
      • 5.6.4 Power and Ground
      • 5.6.5 Resistive Switches
      • 5.6.6 Delay Specification on Switches
    • 5.7 Example Programs – Structural Gate Level Modeling
      • 5.7.1 Half Adder
      • 5.7.2 Full Adder (1-bit Adder)
      • 5.7.3 Ripple Carry Adder (4-bit Adder)
      • 5.7.4 Decoder
      • 5.7.5 Equality Detector
      • 5.7.6 Comparator (2-bit Magnitude Comparator)
      • 5.7.7 Priority Encoder
      • 5.7.8 D Latch
      • 5.7.9 D Flip-flop
    • Review Questions
      • Short Questions
      • Brief Questions
  • SOLV ED QUESTION PAPERS
    • B.E/B.Tech. Degree Examination, Nov/Dec 2011
    • B.E/B.Tech. Degree Examination, April/May 2011 (Regulation2008)
    • B.E/B.Tech. Degree Examination, April/May 2011 (Regulation 2011)
    • B.E/B.Tech. Degree Examination, April/May 2010
    • B.E/B.Tech. Degree Examination, Nov/Dec 2009
    • B.E/B.Tech. Degree Examination, May/June 2009
    • B.E/B.Tech. Degree Examination, Nov/Dec 2008
    • B.E/B.Tech. Degree Examination, April/May 2008
    • B.E/B.Tech. Degree Examination, Nov/Dec 2007
  • GLOSSARY
  • INDEX
Biographical note

Dr. Jose Anand is Associate Professor, Department of Electronics and Communication, KCG College of Technology, Chennai. He obtained his Bachelors in Engineering from Institution of Engineers (India), Masters in Embedded Systems from Anna University, MBA from Alagappa University, and completed his Doctrate from Anna University.

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