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Digital Electronics  
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ISBN: 9789394524132

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Description

Table of contents

Biographical note

This book is designed for a comprehensive coverage of all the new syllabus regulation 2017, as prescribed by Anna University for the third semester ECE students.

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Description

This book is designed for a comprehensive coverage of all the new syllabus regulation 2017, as prescribed by Anna University for the third semester ECE students.

Table of contents
  • Cover
  • Title Page
  • Copyright Page
  • Dedication
  • About the Authors
  • Syllabus
  • Contents
  • Preface
  • Acknowledgements
  • Chapter 1 Overview of Number Systems
    • 1.1 Introduction
    • 1.2 Digital Signals
      • 1.2.1 Why are Binary Numbers Used?
      • 1.2.2 What is a Digital Signal?
    • 1.3 Number Systems
    • 1.4 Base Conversions
      • 1.4.1 Binary to Decimal Conversion
      • 1.4.2 Decimal to Binary Conversion
      • 1.4.3 Decimal to Base-r
      • 1.4.4 Base-r to Decimal
      • 1.4.5 Binary to Octal and Hexadecimal Conversion
      • 1.4.6 Conversion from Hexadecimal to Octal and vice versa
    • 1.5 Complements
      • 1.5.1 r’s Complement or Radix Complement
      • 1.5.2 (r–1)’s Complement or Diminished Radix Complement
      • 1.5.3 Additional Method to Determine and Complements
    • 1.6 Signed Binary Numbers
    • 1.7 Binary Arithmetic
    • Binary Addition
    • Binary Subtraction
    • Binary Multiplication
    • Binary Division
    • 1.8 Complement/1’s Complement Arithmetic
      • 1.8.1 Subtraction with Complements
      • 1.8.2 Subtraction with 1’s Complement
    • Summary
    • Review Questions
    • Problems
  • Chapter 2 Minimization Techniques
    • 2.1 Introduction
    • 2.2 Boolean Postulates and Laws
      • 2.2.1 Basic Definitions and Properties of Boolean Algebra
      • 2.2.2 Principle of Duality
      • 2.2.3 Proof of Theorems
      • 2.2.4 Simplification Theorem
    • 2.3 Boolean Expression
      • 2.3.1 Representation of Boolean Expression
    • 2.4 Canonical and Standard Forms
      • 2.4.1 Minterms and Maxterms
      • 2.4.2 Sum of Minterms
      • 2.4.3 Product of Maxterms
      • 2.4.4 Conversion Between Canonical Forms
      • 2.4.5 Standard Forms
      • 2.4.6 Worked Out Examples
      • 2.4.7 Other Logic Operations
    • 2.5 Karnaugh Map Minimization
      • 2.5.1 Two and Three Variables Maps
      • 2.5.2 Four Variable Map
      • 2.5.3 Representation of Truth Table on K-Map
      • 2.5.4 Obtaining Truth Table From K-Map
      • 2.5.5 Representation of SOP and POS Form on K-Map
    • 2.6 Simplification Of Logical Functions Using K-Map
      • 2.6.1 Simplification Using Three Variable K-Map
      • 2.6.2 Simplification Using Four Variable K-Map
    • 2.7 Don’t Care Condition
    • 2.8 Prime Implicants and Essential Prime Implicants
    • 2.9 Five Variables Map
    • 2.10 Six Variable Map
    • 2.11 Variation of Maps
    • 2.12 The Tabulation Method or Quine-Mcclusky Method
      • 2.12.1 Determination of Prime Implicants in Tabulation Method
      • 2.12.2 Another Approach – Decimal Number Comparison
      • 2.12.3 Comparison Process
    • 2.13 Worked Out Examples
    • Summary
    • Review Questions
    • Problems
  • Chapter 3 Logic Gates
    • 3.1 Introduction
    • 3.2 Basic Digital Circuits
      • 3.2.1 AND Operation
      • 3.2.2 OR Operation
      • 3.2.3 NOT Operation
      • 3.2.4 NAND and NOR Operations
      • 3.2.5 Ex-OR and Ex-NOR Operations
    • 3.3 Implementations of Logic Functions Using Gates
    • 3.4 NAND-NOR Implementation
      • 3.4.1 Realization of Logic Gates Using NAND and NOR
      • 3.4.2 Graphical Symbol
      • 3.4.3 Two Level Implementation
      • 3.4.4 Multilevel Realization
      • 3.4.5 Wired Logic
      • 3.4.6 Multi Output Gate Implementations
    • 3.5 Introduction to Digital Logic Families
      • 3.5.1 Classification
      • 3.5.2 Transistor-Transistor Logic (TTL)
      • 3.5.3 Emitter-Coupled Logic (ECL)
      • 3.5.4 MOS and CMOS
      • 3.5.5 Tristate Gates
      • 3.5.6 Characteristics of Digital IC
      • 3.5.7 Current and Voltage Parameters
    • Summary
    • Review Questions
    • Problems
  • Chapter 4 Combinational Logic Circuits
    • 4.1 Introduction
    • 4.2 Analysis and Design Procedure
      • 4.2.1 Analysis Procedure
      • 4.2.2 Design Procedure
    • 4.3 Adders/Subtractors
      • 4.3.1 Half Adder and Half Subtractor
      • 4.3.2 Full Adder and Full Subtractor
      • 4.3.3 Binary Parallel Adder
      • 4.3.4 Binary Parallel Subtractor
      • 4.3.5 Binary Adder/Subtractor
      • 4.3.6 Look-Ahead Carry Adder: Fast Adder
      • 4.3.7 Serial Adder/Subtractor
      • 4.3.8 Decimal Adder/Subtractor or BCD Adder
    • 4.4 Binary Multiplier/Divider
    • 4.5 Multiplexer
      • 4.5.1 Boolean Function Implementation Using MUX
      • 4.5.2 Interconnection of Multiplexers
    • 4.6 Demultiplexer
      • 4.6.1 Expansion of DEMUX and Implementation of Boolean Function
    • 4.7 Decoders and Encoders
      • 4.7.1 Decoders
      • 4.7.2 Three to Eight Line Decoder
      • 4.7.3 BCD to Seven Segment Decoder
      • 4.7.4 Encoder
      • 4.7.5 Priority Encoder
    • 4.8 Parity Generator/Checker
      • 4.8.1 Parity Generator
      • 4.8.2 Parity Checker
    • 4.9 Code Conversion
      • 4.9.1 Binary to Gray Code and Gray Code to Binary Conversion – Direct Method
      • 4.9.2 Binary to Gray Code and Gray Code to Binary Conversion – Conventional Method
      • 4.9.3 Binary to BCD
      • 4.9.4 BCD to Binary Conversion
      • 4.9.5 Eight – bit BCD to Binary Conversion
      • 4.9.6 BCD to Excess-3 Code Conversion
      • 4.9.7 Excess-3 to BCD Code Converter
    • 4.10 Magnitude Comparator
      • 4.10.1 One-bit Magnitude Comparator
      • 4.10.2 Two-bit Magnitude Comparator
      • 4.10.3 Four-bit Magnitude Comparator
    • 4.11 Functionally Complete Set
    • Summary
    • Review Questions
    • Problems
  • Chapter 5 Latches and Flip-Flops
    • 5.1 Introduction
    • 5.2 A One-Bit Memory Cell
    • 5.3 S-R Flip-Flop
      • 5.3.1 S-R Latch with NAND Gate
      • 5.3.2 NOR S-R Latch
      • 5.3.3 Clocked S-R Latch (S-R Flip-Flop)
      • 5.3.4 Characteristic Equation
      • 5.3.5 Timing Diagram
      • 5.3.6 Preset and Clear
    • 5.4 J-K Flip-Flop
      • 5.4.1 Characteristic Equation
      • 5.4.2 Timing Diagram
      • 5.4.3 Race Around Condition
      • 5.4.4 Master Slave Flip-Flop
    • 5.5 Delay Flip-Flop
      • 5.5.1 Characteristic Equation
    • 5.6 T Flip-Flop
      • 5.6.1 Characteristic Equation
    • 5.7 Flip-Flop Excitation Tables
    • 5.8 Conversion of Flip-Flop From one Type to Another Type
    • 5.9 Triggering in Flip-Flop
    • 5.10 Edge Triggered S-R Flip-Flop
    • 5.11 Level Triggered S-R Flip-Flop
    • 5.12 Applications of Flip-Flops
    • Summary
    • Review Questions
    • Problems
  • Chapter 6 Synchronous Sequential Circuit
    • 6.1 Introduction
    • 6.2 Sequential Circuit Model
    • 6.3 Terms and Definitions Used in Sequential Circuit
    • 6.4 Analysis of Synchronous Sequential Circuits
      • 6.4.1 Analysis Procedure
    • 6.5 Synthesis Synchronous Sequential Circuit
      • 6.5.1 Design Procedure
      • 6.5.2 State Reduction
      • 6.5.3 State Assignment
    • Summary
    • Review Questions
    • Problems
  • Chapter 7 Registers and Counters
    • 7.1 Introduction
    • 7.2 Registers
      • 7.2.1 Shift Registers
      • 7.2.2 Serial In Serial Out [SISO] Shift Register
      • 7.2.3 Serial In Parallel Out [SIPO] Shift Register
      • 7.2.4 Parallel In Serial Out [PISO] Shift Register
      • 7.2.5 Parallel In Parallel Out [PIPO] Shift Register
      • 7.2.6 Bidirectional Shift Register
    • 7.3 Universal Register
    • 7.4 Applications of Shift Register
      • 7.4.1 Serial Adder/Subtractor
    • 7.5 Shift Register Counters
      • 7.5.1 Ring Counter
      • 7.5.2 Johnson Counter/Shift Counter
    • 7.6 Counters
      • 7.6.1 Ripple Counter
      • 7.6.2 UP/DOWN Counter
      • 7.6.3 Three Bit Binary Ripple Counter
    • 7.7 Modulus of Counter
      • 7.7.1 Mod–5 Counter
      • 7.7.2 Mod–10 Counter or Decade Counter
    • 7.8 Synchronous Counter
      • 7.8.1 Three Bit Synchronous Counter
      • 7.8.2 UP/DOWN Counter
    • 7.9 Design of Counter
    • 7.10 Sequence Generator
    • 7.11 Programmable Counter
    • Summary
    • Review Questions
    • Problems
  • Chapter 8 Memory and Programmable Logic Device
    • 8.1 Introduction
    • 8.2 Read Only Memory – ROM
      • 8.2.1 Architecture of ROM
      • 8.2.2 Classification of ROM
    • 8.3 Random Access Memory – RAM
      • 8.3.1 Basic Terms and Definition
      • 8.3.2 Memory Unit
      • 8.3.3 Classifications of RAM
    • 8.4 Memory Decoding
      • 8.4.1 Coinciding Decoding
      • 8.4.2 Address Multiplexing
    • 8.5 Memory Expansion
    • 8.6 Programmable Logic Device (PLD)
      • 8.6.1 ROM as a PLD
      • 8.6.2 PLD Using Array Logic Diagram
    • 8.7 Programmable Logic Array (PLA)
      • 8.7.1 Structure of PLA
    • 8.8 Programmable Array Logic [PAL]
    • 8.9 Sequential Programmable Device
      • 8.9.1 SPLD
      • 8.9.2 CPLD
      • 8.9.3 FPGA
    • Summary
    • Review Questions
    • Problems
  • Chapter 9 Asynchronous Sequential Circuit
    • 9.1 Introduction
    • 9.2 Terms and Definitions Used in Asynchronous Sequential Circuit
    • 9.3 Analysis of Asynchronous Sequential Circuit
      • 9.3.1 Fundamental Mode Circuit without Latches
      • 9.3.2 Circuit with Latches
      • 9.3.3 Implementation of Sequential Circuit with SR Latch
    • 9.4 Design of Asynchronous Sequential Circuit
      • 9.4.1 Primitive Flow Table
    • 9.5 State Reduction Techniques
      • 9.5.1 State Reduction of Completely Specified States
      • 9.5.2 State Reduction of Incompletely Specified States
    • 9.6 State Assignment and Unspecified Output Assignment
      • 9.6.1 Races and Cycles
      • 9.6.2 Race Free State Assignments
      • 9.6.3 Unspecified Output Assignment
    • 9.7 Hazards
      • 9.7.1 Circuits with Hazard
      • 9.7.2 Hazard Free Circuit
      • 9.7.3 Effect of Hazards in Asynchronous Sequential Circuit
      • 9.7.4 Essential Hazards
    • 9.8 Design Example
    • Summary
    • Review Questions
    • Problems
  • Chapter 10 Algorithm State Machine and Verilog Hdl
    • 10.1 Introduction
    • Need for ASM
    • Usage of ASM
    • Flowcharts of ASM
    • 10.2 ASM (Algorithmic State Machine) Charts
    • ASM Chart Rules
    • ASM Block
    • 10.3 Design Phases
    • Moore State Machine
    • 10.4 Introduction
    • Features
    • Major Design Steps
    • Design Entry
    • Logic Simulation
    • Logic Synthesis and Timing Verification
    • Fault Simulation
    • Types of HDL
    • 10.5 Verilog HDL
    • Starting with Verilog – Module and Some Important Keywords
    • Gate Delay
    • Test Bench
    • Boolean Equations
    • User Defined Primitives (UDP)
    • 10.6 HDL for Combinational Circuits
    • 10.6.1 HDL Description of Combination Circuit Using Gate Level Modeling
    • 10.6.2 Modeling with Vector Data
    • 10.6.3 HDL Description of Combination Circuit Using Data Flow Level Modeling
    • 10.6.4 HDL Description of Combination Circuit Using Behavioral Modeling
    • 10.7 HDL for Sequential Logic Circuits
    • Summary
    • Review Questions
    • Problems
  • Two Mark Questions and Answers
  • Solved Question Papers
    • April/May 2011 SP.3
    • Nov/Dec 2011 SP.17
    • May/June 2012 SP.31
    • Nov/Dec 2012 SP.39
    • May/June 2013 SP.53
    • Nov/Dec 2013 SP.64
  • References
  • Index
Biographical note

Sanjay Kumar Suman is currently Assistant Professor, Department of Electronics and Communication Engineering, Easwari Engineering College, Chennai.

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